The present invention relates to delay circuits and, more particularly, to delay line circuits having an adjustable delay step and a delay cell for the same.
A delay line is a circuit that is used to delay transmission of a signal, such as a clock signal, for a desired amount of time, and is typically constructed by connecting a plurality of delay cells in series. The accuracy of the delay provided is generally tightly controlled to assure proper circuit operation in high data rate devices, such as a Double Data Rate (DDR) random access memory (RAM). Generally, the higher the operating speed of a DDR RAM, the smaller the delay step or the step size of each delay cell must be. As such, where a greater the number of delay cells ate included in the delay line, a corresponding greater number of bits of a signal controlling the delay cells are provided. Accordingly, the delay step of the delay line generally must be more accurately adjusted for such an application.